Single-Slot FHHL PCIe SmartNIC with Intel Stratix 10 GX 400 FPGA, 4x 10 GigE (MLE-NPAC-Ketch 40G P2201v2)

Note: the Minimum order Quantity is 10 units.

The MLE MLE-NPAC-Ketch 40G P2201v2 is a Single-Slot FHHL PCIe SmartNIC integrating an Intel Stratix 10 GX 400 FPGA, 4x SFP for 4x 10 GigE, a FPGA-attached DDR4 DRAM via SO-DIMM and with 50 Watts TDP passivecooling front-to-back. It provides 40 Gbps Source-to-Sink Data Transport, a full accelerato to fully offload the CPU, and cost-efficient, customizable and ready-to-run.

Features

• Intel Stratix 10 GX 400 FPGA
• FHHL PCIe Card
• PCIe 3.1 x8 (~60 Gbps bandwidth)
• 4x 10 Gigabit Ethernet via SFP+
• IETF 1122 TCP/UDP/IP Stack from FhG HHI
• IPv4 with ICMP, IGMP, DHCP, ARP
• In-Network Processing Custom User Logic
• Corundum.io MQNIC (optional)
• IEEE 802.1AS PTPv2 (optional)
• IEEE 802.1Qav 802.1Qbv Traffic Shaping
• Technical Specification
  • Total Electrical Load & Thermal: 60 W, 50 W TDP passive cooling front-to-back
  • Form Factor: PCI-SIG CEM Rev 3.0 FHHL
  • On-Board Memory: FPGA-attached DDR4 DRAM via SO-DIMM
  • Network Function Support: IETF 1122 TCP/UDP/IP plus Linux 4.18 and 5.10
  • Performance Metrics
    • 128 bit wide bi-directional data paths with AXI4-Stream interfaces
    • TCP/UDP/IP processing at full 40 Gbps line rate
    • Door-to-door latency of 656 ns for 160 Bytes

Development Support

• Latest documentation, design support files and reference designs with source files are available for download free of charge.

Scope of Delivery

• 10x MLE-NPAC-Ketch 40G P2201v2
  
  • Pre-configured PCIe Card, ready-to-run
  • Linux device drivers (GPL sources)
  • FPGA Design Project with NPAP design license for adding Custom User Logic (optional)
  • Application-specific expert design services (optional)

References

• Manufacturer: Missing Link Electronics (MLE) 
• Manufacturer's article name: Single-Slot FHHL PCIe SmartNIC with Intel Stratix 10 GX 400 FPGA, 4x 10 GigE
• Manufacturer's article number: MLE-NPAC-Ketch 40G P2201v2

Resources

• Schematics (Available upon request)
• Assembly Diagrams (Available upon request)
• Programming files of CPLD Firmware (Available upon request)
• Source Code of CPLD Firmware (Available upon request)
• STEP Models (Available upon request)
• Reference Design (Available upon request)